Complexity Issues in Gate Duplication

In this paper we address the complexity issues associated with gate duplication for delay optimization. Gate duplication for general circuits has been proved NP-Complete [1]. In this paper we show that even the local delay optimization by gate duplication is NPComplete. Local fanout optimization (bu er insertion) for xed net topology can be solved in polynomial time [9]. Even the global fanout optimization problem has polynomial time complexity if all the pin to pin parameters of a gate are the same and the topology of all the nets is xed [13]. Hence we show that gate duplication is much harder than bu er insertion.